The present invention relates to a method for manufacturing integrated circuits such as high speed bipolar ICs and high speed BiCMOSICs.
In conventional semiconductor integrated circuit manufacture an isolated region is formed on the semiconductor device in accordance with the practice of forming a trench in the silicon substrate to be filled with polysilicon followed by forming a field oxide layer on the silicon substrate.
The conventional practice of forming an isolation region in a semiconductor device so that a field oxide layer may be fabricated thereon is hereafter described in connection with FIGS. 23 through 30 inclusive.
First, in order to fabricate an n-type epitaxial layer 2, 1.0 .mu.m thick, a 1E16 cm.sup.-3 dopant concentration is formed on the surface of a p-type semiconductor (silicon) substrate and a n-type buried layer 3 of a 1E18 cm.sup.-3 dopant concentration is formed underneath by a known technique. Second, a 50 nm thick first SiO.sub.2 layer 4 is fabricated on the n-type expitaxial layer 2 by an oxidation method. Third, a 1500 nm thick SiN layer 5 and a 1.0 .mu.m thick second SiO.sub.2 layer 6, such as by a CVD (Chemical-Vapor Deposition) method, is fabricated in that order (FIG. 23.)
Now, using a lithography technique, form a resist pattern 7 having a pocket with a 1.0 .mu.m wide opening 8(FIG. 24).
Anisotropically etch through the second SiO.sub.2 layer 6 over the mask of resist pattern 7 to extend the opening 8 to the n-type epitaxial layer 2 (FIG. 25).
Anisotropically etch the silicon substrate to remove 6 .mu.m deep of the substrate using the second SiO.sub.2 layer 6 as a mask to form a trench 9 (FIG. 26) extending from the first SiO.sub.2 layer 4 with the trench 9 having sidewalls in cross section.
Next, oxidize the sidewalls of the trench 9 to form a third SiO.sub.2 layer 10 using a conventional oxidization method. Deposit a first polysilicon layer 11a in the trench 9 and using the second SiO.sub.2 layer 6 as an etch buffer layer etchback the first polysilicon layer 11a (FIG. 27).
Remove the exposed second SiO.sub.2 layer 6 using buffered oxygen fluoride (FIG. 28); then etchback the first polysilicon layer 11a using the SiN layer 5 as an etch buffer layer by a CMP (Chemical-Mechanical Polishing) method to complete filling of the trench (FIG. 29). Then, form a desired pattern on the SiN layer 5 by a known technique.
Finally, form a 500 nm thick field oxide layer 13 over the n-type epitaxial layer 2 and the first polysilicon layer 11a (FIG. 30).
At this time, a concavity is formed on the surface of the field oxide layer 13 on top of the third SiO.sub.2 layer 10 against the trench sidewall; two vertical bird's beaks 14 are also formed on top of the third SiO.sub.2 layer 10. The vertical bird's beaks are defects in the surface of field oxide layer 13 equivalent to that of a gouge.
In the process of producing a conventional semiconductor following the aforementioned steps it is believed that because of the third SiO.sub.2 layer 10 that exists, that the trench sidewalls induces formation of the aforementioned vertical bird's beaks 14 at the point where the third SiO.sub.2 layer 10 and the field oxide layer 13 meet during LOCOS oxidation. Upon formation of the field oxide layer two corresponding bird's beaks 14 are produced on top of the third SiO.sub.2 layer. As a result, when etch-patterning a conductive layer to introduce electrodes in a step subsequent to the LOCOS oxidation, the concavity tends to generate etch residues from the conductive layer; this is particularly true in anisotropic etching, inducing interconnect shorting due to the current flowing through the residues. In conventional technology, the etch residues in the bird's beaks 14 are removed by excessive etching.
The vertical bird's beaks 14 are generated either during oxidation of the semiconductor substrate 1 or when the first polysilicon layer 11a is filled into the trench 9 due to oxygen diffusing into the third SiO.sub.2 layer 10 against the trench sidewall during LOCOS oxidation; wherein the vertical bird's beaks 14 accompanies volume expansion generating stress on top of the trench. This stress is one of the factors that cause crystalline defects in the semiconductor substrate 1.
In the conventional method of manufacturing a semiconductor device, vertical bird's beaks are created on top of the trench when forming a trench device isolation region; the vertical bird's beaks induce shorting between interconnects, generating crystalline defects in the semiconductor substrate 1.
The present invention intends to resolve the above problem in the manufacture of a semiconductor device by preventing the generation of vertical bird's beaks to avoid shorting between interconnects in the semiconductor device due to etch residues from a conductive layer, and to prevent generation of crystalline defects on semiconductor substrates, etc.